Delayed branches versus dynamic branch prediction in a high-performance superscalar architecture
Egan, C., Steven, F.L. and Steven, G.B.
(1997)
Delayed branches versus dynamic branch prediction in a high-performance superscalar architecture.
Institute of Electrical and Electronics Engineers (IEEE).
While delayed branch mechanisms were popular with the designers of RISC processors, most superscalar processors deploy dynamic branch prediction to minimise run-time branch penalties. We propose a generalised branch delay mechanism that is more suited to superscalar processors. We then quantitatively compare the performance of our delayed branch mechanism with run-time branch prediction, in the context of a high-performance superscalar architecture that uses aggressive compile-time instruction scheduling.
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Date Deposited | 26 Jul 2024 15:05 |
Last Modified | 26 Jul 2024 15:05 |
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